In conventional (e.g., RF) communication receivers in TDMA systems, the actual RSSI (received signal strength indication) is determined, for example, during a specific period (training sequence) of a communication burst. The RSSI is reported to a DSP or microcontroller (i.e., the baseband processor), which executes a program that uses the RSSI to calculate the optimum AGC setting. This intervention by the microcontroller or DSP slows the process of setting the AGC. This is particularly disadvantageous in some situations.
For example, fast antenna diversity control at high ISN band frequencies (above 2 GHz) can be very advantageous. A slow AGC setting process impedes fast antenna diversity control. As another example, in license free bands, there is typically a need for high receiver linearity. One factor in achieving high receiver linearity is an optimum AGC setting. However, because an optimum AGC is required, the process of setting the AGC is further slowed.
Also, the time required for the baseband processor to receive the RSSI information, execute the program to determine the new AGC setting, and report the new AGC setting to the RF front end (e.g. via a serial interface) is so long that the new AGC setting is not available to the RF front end (in the best case) until the next communication burst. This is particularly disadvantageous when the communication involves real time data streaming.
It is therefore desirable to provide for a faster AGC setting than is conventionally available with baseband processor intervention.
According to the invention, a hardware control loop derives the AGC setting from signal strength information without incurring program execution delay of the baseband processor. This advantageously reduces the time required to set the AGC.